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ltc3419 1 3419fa output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 power loss (w) 10 1 0.1 0.01 0.001 0.0001 0.1 10 100 1000 3419 ta01b 1 v out = 1.2v v out = 1.8v v out = 2.5v v in = 3.6v n cellular telephones n digital still cameras n wireless and dsl modems n portable media players n pdas/palmtop pcs features applications description dual monolithic 600ma synchronous step-down regulator the ltc ? 3419 is a dual, 2.25mhz, constant-frequency, synchronous step-down dc/dc converter in a tiny 3mm 3mm dfn package. 100% duty cycle provides low dropout operation, extending battery life in portable systems. low output voltages are supported with the 0.6v feedback reference voltage. each regulator can supply 600ma output current. the input voltage range is 2.5v to 5.5v, making it ideal for li-ion and usb powered applications. supply current during operation is only 35a and drops to <1a in shutdown. a user-selectable mode input allows the user to trade off between high ef? ciency burst mode operation and pulse-skipping mode. an internally set 2.25mhz switching frequency allows the use of tiny surface mount inductors and capacitors. internal soft-start reduces inrush current during start-up. both outputs are internally compensated to work with ceramic output capacitors. the ltc3419 is available in a low pro? le (0.75mm) 3mm 3mm dfn package. the ltc3419 is also available in a ? xed output voltage con? guration selected via internal resistor dividers (see table 2). dual monolithic buck regulator in 8-lead 3 3 dfn n high ef? ciency dual step-down outputs: up to 96% n 600ma current per channel at v in = 3v n only 35a quiescent current during operation (both channels) n 2.25mhz constant-frequency operation n 2.5v to 5.5v input voltage range n low dropout operation: 100% duty cycle n no schottky diodes required n internally compensated for all ceramic capacitors n independent internal soft-start for each channel n available in fixed output versions n current mode operation for excellent line and load transient response n 0.6v reference allows low output voltages n user-selectable burst mode ? operation n short-circuit protected n ultralow shutdown current: i q < 1a n available in small msop or 3mm 3mm dfn-8 packages , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6127815, 6304066, 6498466, 6580258, 6611131. ef? ciency and power loss vs output current v in run2 run1 ltc3419 v fb2 sw2 sw1 mode v fb1 22pf 22pf gnd v in 2.5v to 5.5v v out2 1.8v at 600ma v out1 2.5v at 600ma 3419 ta01 118k 187k 59k 59k 3.3 h3.3 h 10 f 10 f 10 f typical application
ltc3419 2 3419fa absolute maximum ratings input supply voltage (v in ) ............................. ?0.3 to 6v v fb1 , v fb2 ........................................ ?0.3v to v in + 0.3v run1, run2, mode ........................ ?0.3v to v in + 0.3v sw1, sw2 ....................................... ?0.3v to v in + 0.3v p-channel sw source current (dc) (note 2) .......800ma n-channel sw source current (dc) (note 2) ......800ma (note 1) top view dd package 8-lead ( 3mm s 3mm ) plastic dfn 5 6 7 8 9 4 3 2 1v fb1 run1 mode sw1 v fb2 run2 sw2 v in t jmax = 125c, ja = 40c/w exposed pad (pin 9) is gnd, must be soldered to pcb 1 2 3 4 5 v fb1 run1 mode sw1 gnd 10 9 8 7 6 v fb2 run2 sw2 v in gnd top view ms package 10-lead plastic msop t jmax = 125c, ja = 120c/w peak sw source and sink current (note 2) .............1.3a operating junction temperature range (note 3) .................................................?40 to 125c junction temperature (note 6) ............................. 125c storage temperature range ...................?65c to 125c lead temperature (soldering, 10 sec) msop package ................................................. 300c pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc3419edd#pbf ltc3419edd#trpbf lcqj 8-lead (3mm 3mm) plastic dfn ?40c to 125c ltc3419edd-1#pbf ltc3419edd-1#trpbf lcww 8-lead (3mm 3mm) plastic dfn ?40c to 125c ltc3419idd#pbf ltc3419idd#trpbf lcqj 8-lead (3mm 3mm) plastic dfn ?40c to 125c ltc3419idd-1#pbf ltc3419idd-1#trpbf lcww 8-lead (3mm 3mm) plastic dfn ?40c to 125c ltc3419ems#pbf ltc3419ems#trpbf ltcqk 10-lead plastic msop ?40c to 125c ltc3419ems-1#pbf ltc3419ems-1#trpbf ltcwx 10-lead plastic msop ?40c to 125c ltc3419ims#pbf ltc3419ims#trpbf ltcqk 10-lead plastic msop ?40c to 125c ltc3419ims-1#pbf ltc3419ims-1#trpbf ltcwx 10-lead plastic msop ?40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc3419 3 3419fa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: guaranteed by long term current density limitations. note 3: the ltc3419e and ltc3419e-1 are guaranteed to meet speci? ed performance from 0c to 85c. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3419i and ltc3419i-1 are guaranteed to meet speci? ed performance over the full C40c to 125c operating junction temperature range. symbol parameter conditions min typ max units v in v in operating voltage 2.5 5.5 v v uv v in undervoltage lockout v in low to high 2.1 2.5 v i fb feedback pin input current ltc3419 ltc3419-1 3 30 5 na a v fbreg1 regulated feedback voltage (channel 1) ltc3419e, 0c < t j < 85c ltc3419e, C40c < t j < 85c ltc3419e-1, C40c < t j < 85c ltc3419i, C40c < t j < 125c ltc3419i-1, C40c < t j < 125c 0.590 0.588 1.544 0.582 1.533 0.600 0.600 1.575 0.6 1.575 0.610 0.612 1.606 0.618 1.617 v v v v v v fbreg2 regulated feedback voltage (channel 2) ltc3419e, 0c < t j < 85c ltc3419e, C40c < t j < 85c ltc3419e-1, C40c < t j < 85c ltc3419i, C40c < t j < 125c ltc3419i-1, C40c < t j < 125c 0.590 0.588 1.764 0.582 1.753 0.600 0.600 1.8 0.6 1.8 0.610 0.612 1.836 0.618 1.847 v v v v v v line reg reference voltage line regulation v in = 2.5v to 5.5v (note 7) 0.3 0.5 %/v v load reg output voltage load regulation i load = 0ma to 600ma (note 7) 0.5 % i s input dc supply current active mode (note 4) sleep mode shutdown v fb1 = v fb2 = 0.95 v fbreg v fb1 = v fb2 = 1.05 v fbreg , v in = 5.5v run1 = run2 = 0v, v in = 5.5v 500 35 0.1 700 60 1 a a a f osc oscillator frequency v fb = v fbreg 1.8 2.25 2.7 mhz i lim peak switch current limit channel 1 (600ma) channel 2 (600ma) v in = 3v, v fb < v fbreg , duty cycle < 35% 900 900 1200 1200 ma ma r ds(on) channel 1 (note 5) top switch on-resistance bottom switch on-resistance channel 2 (note 5) top switch on-resistance bottom switch on-resistance v in = 3.6v, i sw = 100ma v in = 3.6v, i sw = 100ma v in = 3.6v, i sw = 100ma v in = 3.6v, i sw = 100ma 0.4 0.4 0.4 0.4 0.6 0.6 0.6 0.6 i sw(lkg) switch leakage current v in = 5v, v run = 0v 0.01 1 a t softstart soft-start time v fb from 10% to 90% full scale 0.1 0.95 1.3 ms v run run threshold high 0.4 1 1.2 v i run run leakage current 0.01 1 a v mode mode threshold high 0.4 1 1.2 v i mode mode leakage current 0.01 1 a v burst output ripple in burst mode operation v out = 1.5v, c out = 10f 20 mv p-p electrical characteristics the denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c, v in = 3.6v, unless otherwise noted. note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: the dfn switch on-resistance is guaranteed by correlation to wafer level measurements. note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 7: the converter is tested in a proprietary test mode that connects the output of the error ampli? er to the sw pin, which is connected to an external servo loop.
ltc3419 4 3419fa v in (v) 2.5 leakage current (na) 3.0 2.5 1.5 2.0 1.0 0.5 0 4.0 5.0 3419 g07 3.0 3.5 4.5 5. 5 main switch synchronous switch v in (v) 2.5 r ds(on) () 0.50 0.45 0.35 0.40 0.30 0.25 0.20 4.0 5.0 3419 g08 3.0 3.5 4.5 6. 0 5.5 main switch synchronous switch temperature (c) C50 v fb (% error) 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 25 75 3419 g04 C25 0 50 100 12 5 temperature (c) C50 frequency (mhz) 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.8 1.9 25 75 3419 g05 C25 0 50 100 12 5 v in = 4.2v v in = 3.6v v in = 2.7v temperature (c) C50 supply current (a) 55 50 40 45 30 35 20 25 15 25 75 3419 g06 C25 0 50 125 100 run1 = run2 = v in i load = 0a v in = 5.5v v in = 2.7v v in (v) 2.5 efficiency (%) 100 90 70 80 60 40 50 30 4.0 5.0 3419 g03 3.0 3.5 4.5 5. 5 v out = 1.8v i out = 600ma i out = 100ma i out = 1ma i out = 0.1ma i out = 10ma typical performance characteristics burst mode operation pulse skip mode operation ef? ciency vs input voltage reference voltage vs temperature oscillator frequency vs temperature supply current vs temperature switch leakage vs input voltage switch on-resistance vs input voltage switch on-resistance vs temperature temperature (c) C50 r ds(on) () 0.6 0.5 0.4 0.3 0.2 0.1 25 75 3419 g09 C25 0 50 100 125 synchronous switch main switch v in = 2.7v v in = 3.6v v in = 4.2v v in = 3.6v v out = 1.8v i load = 25ma sw 2v/div i l 100ma/div v out 50mv/div ac-coupled 2s/div 3419 g01 v in = 3.6v v out = 1.8v i load = 5ma sw 2v/div i l 100ma/div v out 50mv/div ac-coupled 5s/div 3419 g02 t a = 25c, v in = 3.6v, unless otherwise noted.
ltc3419 5 3419fa v in (v) 2.5 v out error (%) 0.6 0.4 0 0.2 C0.2 C0.4 C0.6 4.0 5.0 3419 g16 3.0 3.5 4.5 5.5 v out = 1.8v i load = 100ma output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 10 100 100 0 3419 g10 1 v out = 1.2v v in = 2.7v v in = 3.6v v in = 4.2v output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 10 100 100 0 3419 g11 1 v out = 1.8v v in = 2.7v v in = 3.6v v in = 4.2v output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 10 100 100 0 3419 g12 1 v out = 2.5v v in = 2.7v v in = 3.6v v in = 4.2v typical performance characteristics ef? ciency vs load current ef? ciency vs load current ef? ciency vs load current ef? ciency vs load current load regulation load regulation line regulation start-up from shutdown start-up from shutdown output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 10 100 100 0 3419 g13 1 v out = 1.8v pulse skip mode burst mode operation load current (ma) 0 v out error (%) 3.0 2.5 1.5 2.0 0.5 1.0 C0.5 0 C1.0 300 3419 g14 100 200 400 600 500 v out = 1.2v v out = 1.8v v out = 2.5v burst mode operation load current (ma) 0 v out error (%) 2.0 1.5 0.5 1.0 C0.5 0 C1.0 300 3419 g15 100 200 400 600 500 burst mode operation pulse skip mode v out = 1.8v v in = 3.6v v out = 1.8v i load = 0a run 2v/div i l 500ma/div v out 1v/div 250s/div 3419 g17 v in = 3.6v v out = 1.8v r load = 3 run 2v/div i load 500ma/div v out 1v/div 250s/div 3419 g18 t a = 25c, v in = 3.6v, unless otherwise noted.
ltc3419 6 3419fa typical performance characteristics load step load step load step pin functions v fb1 (pin 1/pin 1): regulator 1 output feedback. receives the feedback voltage from the external resistive divider across the regulator 1 output. nominal voltage for this pin is 0.6v. run1 (pin 2/pin 2): regulator 1 enable. forcing this pin to v in enables regulator 1, while forcing it to gnd causes regulator 1 to shut down. mode (pin 3/pin 3): mode select input. to select pulse- skipping mode, tie to v in . grounding this pin selects burst mode operation. do not leave this pin ? oating. sw1 (pin 4/pin 4): regulator 1 switch node connection to the inductor. this pin swings from v in to gnd. v in (pin 5/pin 7): main power supply. must be closely de-coupled to gnd. sw2 (pin 6/pin 8): regulator 2 switch node connection to the inductor. this pin swings from v in to gnd. run2 (pin 7/pin 9): regulator 2 enable. forcing this pin to v in enables regulator 2, while forcing it to gnd causes regulator 2 to shut down. v fb2 (pin 8/pin 10): regulator 2 output feedback. receives the feedback voltage from the external resistive divider across the regulator 2 output. nominal voltage for this pin is 0.6v. exposed pad (pin 9/na): ground. the exposed pad must be soldered to pcb for optimal thermal performance. gnd (na/pins 5, 6): ground. connect to the (C) terminal of c out , and the (C) terminal of c in . pin 5 of the ms package must be soldered to the pc board for optimal thermal performance. (dd/ms) v in = 3.6v v out = 1.8v i load = 0a to 600ma i load 500ma/div i l 500ma/div v out 100mv/div ac-coupled 20s/div 3419 g19 v in = 3.6v v out = 1.8v i load = 40ma to 600ma i load 500ma/div i l 500ma/div v out 100mv/div ac-coupled 20s/div 3419 g20 v in = 3.6v v out = 1.2v i load = 40ma to 600ma i load 500ma/div i l 500ma/div v out 100mv/div ac-coupled 20s/div 3419 g21 t a = 25c, v in = 3.6v, unless otherwise noted.
ltc3419 7 3419fa functional diagram C + C + ea C + v sleep i th switching logic and blanking circuit s r q q rs latch burst C + i comp i rcmp anti shoot- thru slope comp sleep 0.6v ref osc osc regulator 2 (identical to regulator 1) sleep1 sleep2 shutdown regulator 1 sw1 sw2 3419 fd 1 2 7 8 run1 run2 v fb2 v fb1 3 mode 4 v in 5 gnd 9 6 0.6v burst clamp soft-start
ltc3419 8 3419fa operation the ltc3419 uses a constant-frequency, current mode architecture. the operating frequency is set at 2.25mhz. both channels share the same clock and run in-phase. the output voltage is set by an external resistor divider returned to the v fb pins. an error ampli? er compares the divided output voltage with a reference voltage of 0.6v and regulates the peak inductor current accordingly. main control loop during normal operation, the top power switch (p-channel mosfet) is turned on at the beginning of a clock cycle when the v fb voltage is below the reference voltage. the current into the inductor and the load increases until the peak inductor current (controlled by i th ) is reached. the rs latch turns off the synchronous switch and energy stored in the inductor is discharged through the bottom switch (n-channel mosfet) into the load until the next clock cycle begins, or until the inductor current begins to reverse (sensed by the i rcmp comparator). the peak inductor current is controlled by the internally compensated i th voltage, which is the output of the error ampli? er. this ampli? er regulates the v fb pin to the internal 0.6v reference by adjusting the peak inductor current accordingly. light load operation there are two modes to control the ltc3419 at light load currents: burst mode operation and pulse-skipping mode. both automatically transition from continuous operation to the selected mode when the load current is low. to optimize ef? ciency, burst mode operation can be selected by grounding the mode pin. when the load is relatively light, the peak inductor current (as set by i th ) remains ? xed at approximately 60ma and the pmos switch operates intermittently based on load demand. by running cycles periodically, the switching losses are minimized. the duration of each burst event can range from a few cycles at light load to almost continuous cycling with short sleep intervals at moderate loads. during the sleep intervals, the load current is being supplied solely from the output capacitor. as the output voltage droops, the error ampli? er output rises above the sleep threshold, signaling the burst comparator to trip and turn the top mosfet on. this cycle repeats at a rate that is dependent on load demand. for applications where low ripple voltage and constant- frequency operation is a higher priority than light load ef? ciency, pulse-skipping mode can be used by connecting the mode pin to v in . in this mode, the peak inductor current is not ? xed, which allows the ltc3419 to switch at a constant-frequency down to very low currents, where it will begin skipping pulses. dropout operation when the input supply voltage decreases toward the output voltage the duty cycle increases to 100%, which is the dropout condition. in dropout, the pmos switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. an important design consideration is that the r ds(on) of the p-channel switch increases with decreasing input supply voltage (see typical performance characteristics). therefore, the user should calculate the worst-case power dissipation when the ltc3419 is used at 100% duty cycle with low input voltage (see thermal considerations in the applications information section). soft-start in order to minimize the inrush current on the input bypass capacitor, the ltc3419 slowly ramps up the output voltage during start-up. whenever the run1 or run2 pin is pulled high, the corresponding output will ramp from zero to full-scale over a time period of approximately 750s. this prevents the ltc3419 from having to quickly charge the output capacitor and thus supplying an excessive amount of instantaneous current. short-circuit protection when either regulator output is shorted to ground, the corresponding internal n-channel switch is forced on for a longer time period for each cycle in order to allow the inductor to discharge, thus preventing inductor current runaway. this technique has the effect of decreasing switching frequency. once the short is removed, normal operation resumes and the regulator output will return to its nominal voltage.
ltc3419 9 3419fa a general ltc3419 application circuit is shown in figure 1. external component selection is driven by the load requirement, and begins with the selection of the inductor l. once the inductor is chosen, c in and c out can be selected. inductor selection although the inductor does not in? uence the operating frequency, the inductor value has a direct effect on ripple current. the inductor ripple current i l decreases with higher inductance and increases with higher v in or v out : i v fl v v l out o out in =? ? ? ? ? ? ? ? ?() 11 accepting larger values of i l allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. a reasonable starting point for setting ripple current is 40% of the maximum output load current. so, for a 600ma regulator, i l = 240ma (40% of 600ma). the inductor value will also have an effect on burst mode operation. the transition to low current operation begins when the peak inductor current falls below a level set by the internal burst clamp. lower inductor values result in higher ripple current which causes the transition to occur at lower load currents. this causes a dip in ef? ciency in the upper range of low current operation. furthermore, lower inductance values will cause the bursts to occur with increased frequency. inductor core selection different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid applications information figure 1. ltc3419 general schematic or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style inductor to use often depends more on the price versus size requirements, and any radiated ? eld/emi requirements, than on what the ltc3419 requires to operate. table 1 shows some typical surface mount inductors that work well in ltc3419 applications. table 1. representative surface mount inductors manu- facturer part number value max dc current dcr height taiyo yuden cb2016t2r2m cb2012t2r2m cb2016t3r3m 2.2h 2.2h 3.3h 510ma 530ma 410ma 0.13 0.33 0.27 1.6mm 1.25mm 1.6mm panasonic elt5kt4r7m 4.7h 950ma 0.2 1.2mm sumida cdrh2d18/ld 4.7h 630ma 0.086 2mm murata lqh32cn4r7m23 4.7h 450ma 0.2 2mm taiyo yuden nr30102r2m nr30104r7m 2.2h 4.7h 1100ma 750ma 0.1 0.19 1mm 1mm fdk fdkmipf2520d fdkmipf2520d fdkmipf2520d 4.7h 3.3h 2.2h 1100ma 1200ma 1300ma 0.11 0.1 0.08 1mm 1mm 1mm tdk vlf3010at4r7- mr70 vlf3010at3r3- mr87 vlf3010at2r2- m1r0 4.7h 3.3h 2.2h 700ma 870ma 1000ma 0.28 0.17 0.12 1mm 1mm 1mm v in run2 run1 ltc3419 v fb2 sw2 sw1 mode v fb1 c f2 c f1 gnd v in 2.5v to 5.5v v out2 v out1 3419 f01 r4 r2 r3 r1 l2 l1 c out2 c out1 c1 input capacitor (c in ) selection in continuous mode, the input current of the converter is a square wave with a duty cycle of approximately v out /v in . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ii vvv v rms max out in out in ? () where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple cur- rent, i max = i lim C i l /2. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case is commonly used to design because even signi? cant
ltc3419 10 3419fa deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours lifetime. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements of the design. an additional 0.1f to 1f ceramic capacitor is also recommended on v in for high frequency decoupling when not using an all-ceramic capacitor solution. output capacitor (c out ) selection the selection of c out is driven by the required effective series resistance (esr). typically, once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. the output ripple v out is determined by: ? viesr fc out l o out + ? ? ? ? ? ? 1 8 where f o = operating frequency, c out = output capacitance and i l = ripple current in the inductor. for a ? xed output voltage, the output ripple is highest at maximum input voltage since i l increases with input voltage. if tantalum capacitors are used, it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalum. these are specially constructed and tested for low esr so they give the lowest esr for a given volume. other capacitor types include sanyo poscap, kemet t510 and t495 series, and sprague 593d and 595d series. consult the manufacturer for other speci? c recommendations. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. because the ltc3419 control loop does not depend on the output capacitors esr for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. however, care must be taken when ceramic capacitors are used at the input. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in , large enough to damage the part. for more information, see application note 88. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. setting the output voltage the ltc3419 regulates the v fb1 and v fb2 pins to 0.6v during regulation. thus, the output voltage is set by a resistive divider according to the following formula: vv r r out =+ ? ? ? ? ? ? 06 1 2 1 2 .() keeping the current small (< 10a) in these resistors maximizes ef? ciency, but making it too small may allow stray capacitance to cause noise problems or reduce the phase margin of the error amp loop. to improve the frequency response of the main control loop, a feedback capacitor (c f ) may also be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. fixed output versions of the ltc3419 (e.g. ltc3419-1) include an internal resistive divider, eliminating the need for external resistors. the resistor divider is chosen such that the v fb input current is approximately 3a. for these versions the v fb pin should be connected directly to v out . table 2 lists the ? xed output voltages available for the ltc3419. applications information table 2. fixed output voltage versions part number v out1 v out2 ltc3419 adjustable adjustable ltc3419-1 1.575v 1.8v
ltc3419 11 3419fa checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine the phase margin. in addition, feedback capacitors (c f1 and c f2 ) can be added to improve the high frequency response, as shown in figure 1. capacitor c f provides phase lead by creating a high frequency zero with r2 which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a re- view of control loop theory, refer to application note 76. in some applications, a more severe transient can be caused by switching in loads with large (>1f) input capacitors. the discharged input capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed speci? cally for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting. ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. percent ef? ciency can be expressed as: % ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc., are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, four sources usually account for the losses in ltc3419 circuits: 1) v in quiescent current, 2) switching losses, 3) i 2 r losses, 4) other system losses. 1. the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small (<0.1%) loss that increases with v in , even at no load. 2. the switching current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continuous mode, i gatechg = f o (q t + q b ), where q t and q b are the gate charges of the internal top and bottom mosfet switches. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 3. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current ? ows through inductor l, but is chopped between the internal top and bottom switches. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top ) ? (dc) + (r ds(on)bot ) ? (1C dc) applications information hot swap is a trademark of linear technology corporation.
ltc3419 12 3419fa the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses: i 2 r losses = i out 2 ? (r sw + r l ) 4. other hidden losses, such as copper trace and internal battery resistances, can account for additional ef? ciency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. other losses, including diode conduction losses during dead-time, and inductor core losses, generally account for less than 2% total additional loss. thermal considerations in a majority of applications, the ltc3419 does not dissipate much heat due to its high ef? ciency. in the unlikely event that the junction temperature somehow reaches approximately 150c, both power switches will be turned off and the sw node will become high impedance. the goal of the following thermal analysis is to determine whether the power dissipated causes enough temperature rise to exceed the maximum junction temperature (125c) of the part. the temperature rise is given by: t rise = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t rise + t ambient as a worst-case example, consider the case when the ltc3419 is in dropout on both channels at an input voltage of 2.7v with a load current of 600ma and an ambient temperature of 70c. from the typical performance characteristics graph of switch resistance, the r ds(on) of the main switch is 0.6 . therefore, power dissipated by each channel is: p d = i out 2 ? r ds(on) = 216mv given that the thermal resistance of a properly soldered dfn package is approximately 40c/w, the junction temperature of an ltc3419 device operating in a 70c ambient temperature is approximately: t j = (2 ? 0.216w ? 40c/w) + 70c = 87.3c which is well below the absolute maximum junction temperature of 125c. pc board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3419. these items are also illustrated graphically in the layout diagrams of figures 2 and 3. check the following in your layout: 1. does the capacitor c in connect to the power v in (pin 5) and gnd (pin 9) as closely as possible? this capacitor provides the ac current of the internal power mosfets and their drivers. 2. are the respective c out and l closely connected? the (C) plate of c out returns current to gnd and the (C) plate of c in . 3. the resistor divider, r1 and r2, must be connected between the (+) plate of c out1 and a ground sense line terminated near gnd (pin 9). the feedback signals v fb1 and v fb2 should be routed away from noisy components and traces, such as the sw lines (pins 4 and 6), and their trace length should be minimized. 4. keep sensitive components away from the sw pins, if possible. the input capacitor c in and the resistors r1, r2, r3 and r4 should be routed away from the sw traces and the inductors. 5. a ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the gnd pin at a single point. these ground traces should not share the high current path of c in or c out . 6. flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. these copper areas should be connected to v in or gnd. applications information
ltc3419 13 3419fa applications information figure 2. ltc3419 layout diagram (see board layout checklist) figure 3. ltc3419 suggested layout v in run2 run1 ltc3419 v fb2 sw2 sw1 v fb1 c f2 c f1 gnd v in 2.5v to 5.5v v out2 v out1 3419 f02 r3 r1 r4 l2 l1 r2 c out2 c1 c out1 bold lines indicate high current paths mode l1 3419 f03 l2 c in c out1 c out2 v out2 v out1 gnd r2 r1 r3 r4 c f1 c f2 v fb1 run1 mode sw1 v fb2 run2 sw2 v in via to gnd via to v in design example as a design example, consider using the ltc3419 in a portable application with a li-ion battery. the battery provides a v in ranging from 2.8v to 4.2v. the load on each channel requires a maximum of 600ma in active mode and 2ma in standby mode. the output voltages are v out1 = 2.5v and v out2 = 1.8v. start with channel 1. first, calculate the inductor value for about 40% ripple current (240ma in this example) at maximum v in . using a derivation of equation 1: l v mhz ma v v 1 25 2 25 240 1 25 42 18 =? ? ? ? ? ? ? = . .?() ? . . .7 7 h for the inductor, use the closest standard value of 2.2h. a 10f ceramic capacitor should be more than suf? cient for this output capacitor. as for the input capacitor, a typical value of c in = 10f should suf? ce, as the source impedance of a li-ion battery is very low. the feedback resistors program the output voltage. to maintain high ef? ciency at light loads, the current in these resistors should be kept small. choosing 10a with the 0.6v feedback voltage makes r1~60k. a close standard 1% resistor is 59k. using equation 2. r v rk out 2 06 1 1 187 =? ? ? ? ? ? ? = . ? an optional 22pf feedback capacitor (c f1 ) may be used to improve transient response.
ltc3419 14 3419fa v in = 3.6v v out = 1.8v i load = 40ma to 600ma i load 500ma/div i l 500ma/div v out 100mv/div ac-coupled 20s/div 3419 f04c1 v in = 3.6v v out = 2.5v i load = 40ma to 600ma i load 500ma/div i l 500ma/div v out 100mv/div ac-coupled 20s/div 3419 f04c2 using the same analysis for channel 2 (v out2 = 1.8v), the results are: l2 = 1.9h r3 = 59k r4 = 118k c f2 = 22pf figure 4 shows the complete schematic for this example, along with the ef? ciency curve and transient response. figure 4a. design example circuit figure 4b. ef? ciency vs output current figure 4c. transient response applications information v in run2 run1 ltc3419 v fb2 sw2 sw1 mode v fb1 c f2 , 22pf c f1 , 22pf gnd v in 2.5v to 5.5v v out2 1.8v at 600ma v out1 2.5v at 600ma 3419 f04a r4 118k r2 187k r3 59k r1 59k l2 2.2 h l1 2.2 h c out2 10 f c out1 10 f c1 10 f c1, c2, c3: taiyo yuden jmk316bj106ml l1, l2: tdk vlf3010at2r2m1rd load step transient response output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 10 100 1000 1 v out = 1.8v v in = 2.7v v in = 3.6v v in = 4.2v 3419 f04b output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 10 100 1000 1 v out = 2.5v v in = 2.7v v in = 3.6v v in = 4.2v
ltc3419 15 3419fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (dd) dfn 1203 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc msop (ms) 0307 rev e seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side detail a 0.53 0.152 (.021 .006) 0.254 (.010) 0 C 6 typ detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 0.1016 0.0508 (.004 .002) 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max
ltc3419 16 3419fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0309 rev a ? printed in usa related parts typical applications part number description comments ltc3405/ltc3405a 300ma i out , 1.5mhz, synchronous step-down dc/dc converters 95% ef? ciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) = 0.8v, i q = 20a, i sd = <1a, thinsot tm package ltc3406/ltc3406b 600ma i out , 1.5mhz, synchronous step-down dc/dc converters 96% ef? ciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 20a, i sd = <1a, thinsot package ltc3407/ltc3407-2 dual 600ma/800ma i out , 1.5mhz/ 2.25mhz, synchronous step-down dc/dc converters 95% ef? ciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 40a, i sd = <1a, ms10e and dfn packages ltc3409 600ma i out , 1.7mhz/2.6mhz, synchronous step-down dc/dc converter 96% ef? ciency, v in(min) = 1.6v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 65a, i sd = <1a, dfn package ltc3410/ltc3410b 300ma i out , 2.25mhz, synchronous step-down dc/dc converters 95% ef? ciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) = 0.8v, i q = 26a, i sd = <1a, sc70 package ltc3411 1.25a i out , 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) = 0.8v, i q = 60a, i sd = <1a, ms10 and dfn packages ltc3412 2.5a i out 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) = 0.8v, i q = 60a, i sd = <1a, tssop-16e package ltc3441/ltc3442, ltc3443 1.2a i out 2mhz, synchronous buck-boost dc/dc converters 95% ef? ciency, v in(min) = 2.4v, v in(max) = 5.5v, v out(min) : 2.4v to 5.25v, i q = 50a, i sd = <1a, dfn package ltc3531/ltc3531-3/ ltc3531-3.3 200ma i out , 1.5mhz, synchronous buck-boost dc/dc converter 95% ef? ciency, v in(min) = 1.8v, v in(max) = 5.5v, v out(min) : 2v to 5v, i q = 16a, i sd = <1a, thinsot and dfn packages ltc3532 500ma i out , 2mhz, synchronous buck-boost dc/dc converter 95% ef? ciency, v in(min) = 2.4v, v in(max) = 5.5v, v out(min) : 2.4v to 5.25v, i q = 35a, i sd = <1a, ms10 and dfn packages ltc3547/ltc3547b dual 300ma i out , 2.25mhz, synchronous step-down dc/dc converters 95% ef? ciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) : 0.6v, i q = 40a, i sd = <1a, dfn-8 package ltc3548/ltc3548-1/ ltc3548-2 dual 400ma and 800ma i out , 2.25mhz, synchronous step-down dc/dc converters 95% ef? ciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) : 0.6v, i q = 40a, i sd = <1a, ms10e and dfn packages ltc3561 1.25a i out , 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) : 0.8v, i q = 240a, i sd = <1a, dfn package thinsot? is a trademark of linear technology corporation. dual 600ma buck converter v in run2 run1 ltc3419 v fb2 sw2 sw1 mode v fb1 c f2 , 22pf c f1 , 22pf gnd v in 2.5v to 5.5v v out2 1.8v at 600ma v out1 2.5v at 600ma 3419 ta02 r4 118k r2 187k r3 59k r1 59k l2 3.3 h l1 3.3 h c out2 10 f c out1 10 f c1 10 f c1, c2, c3: taiyo yuden jmk316bj106ml l1, l2: tdk vlf3010at3r3m1rd 1.8v/1.575v dual 600ma buck converter v in run2 run1 ltc3419-1 v fb2 sw2 sw1 mode v fb1 gnd v in 2.5v to 5.5v v out2 1.8v at 600ma v out1 1.575v at 600ma 3419 ta03 l2 3.3 h l1 3.3 h c out2 10 f c out1 10 f c1 10 f c1 , c2 , c3: taiyo yuden jmk316bj106ml l1 , l2: tdk vlf3010at3r3m1rd

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